GFSK receiver

ABSTRACT

A method for synchronizing a receiver to a stream of transmitted symbols that includes a known synchronization word. The method includes receiving a signal in which the symbols, including the synchronization word, are encoded by frequency shift keying. The signal is sampled and digitized to generate a sequence of input samples. For each of the input samples, a phase difference is determined relative to a preceding input sample in the sequence, thereby generating a sequence of differential samples corresponding respectively to the input samples. The differential samples are then matched to the synchronization word.

FIELD OF THE INVENTION

[0001] The present invention relates generally to wireless communicationdevices, and specifically to receivers for use in high-speed wirelessdigital communications.

BACKGROUND OF THE INVENTION

[0002] Bluetooth™ is a wireless technology designed to allow instant,short-range digital connections to be made between different electronicdevices, replacing the cables that connect current devices. TheBluetooth radio is built into a microchip and operates in the unlicensed2.4 GHz band. Frequency-hop transceivers are used to combat interferenceand fading. Information is exchanged in packets, with each packettransmitted on a different hop frequency. The data bits are encodedusing Gaussian Frequency Shift Keying (GFSK), a shaped, binary frequencymodulation scheme aimed at minimizing transceiver complexity. Thespecified symbol rate is 1 million symbols per second (1 Ms/s).Technical aspects of Bluetooth are described in detail in the Bluetoothspecification, which is available at www.bluetooth.com and isincorporated herein by reference.

[0003] A receiver for use in a Bluetooth environment amplifies signalsthat it receives from the transmitter and downconverts them to basebandfor demodulation. The amplification is typically controlled by anautomatic gain control (AGC) circuit, as is known in the art. Inaddition, the receiver preferably generates a receiver signal strengthindicator (RSSI) signal, which is returned to the transmitter for use incontrolling the transmitted power. To demodulate the signals, thereceiver must be synchronized with the timing and frequency offset ofthe transmitted signal. For this purpose, Bluetooth packets have anaccess code header that includes a 64-bit synchronization word (syncword). The receiver must detect the sync word in order to generate therequired timing and frequency adjustments. Once the receiver issynchronized, it demodulates the digitized signals to recover the binarysymbol stream of ones and zeroes.

[0004] Various methods are known in the art for demodulation offrequency shift-keyed (FSK) signals. The simplest method (which has beenimplemented in early Bluetooth receivers) is analog discrimination ofthe frequency changes in the signal. Coherent, digital demodulationmethods, however, provide better performance in conditions of lowsignal/noise ratio (SNR) and high intersymbol interference (ISI). Anexemplary method of this type is described by Morelli et al., in “JointPhase and Timing Recovery with CPM Signals,” published in IEEETransactions on Communications 45:7 (1997), pages 867-876, which isincorporated herein by reference. The authors propose a general methodfor processing continuous-phase modulation (CPM) signals, noting thatthe method is particularly advantageous in continuous-phasefrequency-shift keying (a class of FSK that includes GFSK). According tothe method of Morelli et al., digitized signals are processed using amaximum likelihood method to determine the correct carrier phase andtiming. The phase and timing are then used in coherent demodulation ofthe signals.

SUMMARY OF THE INVENTION

[0005] It is an object of some aspects of the present invention toprovide an improved receiver for FSK signals, and particularly GFSKsignals sent over a wireless link.

[0006] It is a further object of some aspects of the present inventionto provide an improved method for sync word detection in a FSK signal,and particularly a method that is not sensitive to frequency offset ofthe signal.

[0007] It is yet a further object of some aspects of the presentinvention to provide an improved method for automatic frequency controlof a radio receiver.

[0008] It is still a further object of some aspects of the presentinvention to provide an improved method for demodulation of a FSKsignal.

[0009] It is another object of some aspects of the present invention toprovide improved methods and circuits for automatic gain control in aradio receiver.

[0010] In preferred embodiments of the present invention, a digitalwireless receiver processes and demodulates GFSK signals using apartially coherent demodulation scheme. Each symbol in the receivedsignal is demodulated by calculating correlations between a segment ofthe signal that contains the current symbol and a plurality of differentsymbol sequences that could correspond to the segment. In other words, atime window is defined, preferably centered on the current symbol, andthe correlations are performed on the segment of the signal contained inthe window. Most preferably, the window contains three symbols beforeand three symbols after the current symbol, although other window sizesmay also be used. While the three symbols preceding the current symbolhave already been determined, the current symbol and the threesucceeding symbols are still undetermined. Therefore, the correlationcalculation is performed for each of the different possible combinationsof values of the current symbol and the succeeding symbols in thewindow. In the present exemplary embodiment, using GFSK modulation and awindow that looks ahead four symbols, sixteen correlations must becalculated to decode each symbol. The current symbol is decoded bychoosing the combination having the highest correlation value. Thewindow is then moved ahead one symbol, and the process is repeated.

[0011] Optionally, the decoded current symbol value can be used inrecalculating the correlation values for the preceding symbols. Such arecalculation may be useful in correcting errors that occurred indecoding earlier symbols, but at the cost, or course, of increasedcomputational complexity.

[0012] In some preferred embodiments of the present invention, thesignals sent to the receiver include a known sync word, such as the syncword provided by the above-mentioned Bluetooth standard, which precedesthe actual data that must be demodulated. The receiver detects the syncword in order to find the appropriate timing, frequency and fadingadjustments to use in subsequent demodulation of the data. For thispurpose, the receiver samples the signal and then takes the differencebetween each sample and the next. The differential samples arecorrelated with the known sync word until a match is found that gives amaximum value of the correlation. While matched filtering is known inthe art for correlating a signal with a known template, the matchedfiltering technique is by itself very sensitive to frequency offset anddrift between the transmitter and the receiver, which commonly occurs insystems such as Bluetooth. By using the differential samples, preferredembodiments of the present invention eliminate this frequency offset,enabling the receiver to achieve consistently accurate sync worddetection.

[0013] In preferred embodiments of the present invention, the receivercomprises an automatic frequency control (AFC) circuit, which applies aphase rotation to the input signal before demodulation in order tocorrect for frequency errors. First, an initial AFC setting isdetermined, typically based on sync word detection, as described above.Thereafter, the AFC circuit preferably uses the decision output of thereceiver to detect and correct for small frequency drifts that may occurduring transmission. The drift is detected using groups of successivesymbol decision outputs, together with the samples of the signal thatwere used in the correlation operations for determining the outputs. Thephase deviation between the samples, relative to the decision outputs,gives an estimate of the frequency drift. The drift is preferablyaccumulated using a loop filter, and the filter output is used tocorrect the phase rotation of the input signal to the demodulator.

[0014] While the Bluetooth standard provides a header (including thesync word) at the beginning of each data packet, it does not provide anytail bits at the end of the packet. Therefore, at the end of the packet,the signal amplitude typically drops abruptly. This drop-off may causeerrors in demodulating the signal at the end of the packet. When thepacket ends with an error detection code, such as a cyclic redundancycheck (CRC) code, as is common practice, a bit error at the end of thepacket can result in a CRC error, causing the entire packet to bediscarded. Therefore, some preferred embodiments of the presentinvention provide mechanisms for overcoming the uncertainty that mayoccur in the bits at the tail end of the packet. In one such preferredembodiment, when the CRC check (or other error detection procedure) isperformed, the last bit or bits in the packet are allowed to take oneither of the values zero and one. In other words, two or morealternative error checks are performed, corresponding to the alternativeending bits of the packet. As long as one of the checks returns apositive result, the packet is considered to be valid.

[0015] In another preferred embodiment, the point in the signal thatcorresponds to the last bit in the packet is detected based on the knownpacket length, which is specified in the packet header. Following thislast bit, a number of constant-valued samples are injected into thedemodulator as artificial tail bits, to enable accurate demodulation ofthe signal up to the last actual bit in the packet.

[0016] In some preferred embodiments of the present invention, a novelautomatic gain control (AGC) circuit is used to control theamplification of the input signals in the receiver. While AGC circuitsare well known in the art, the Bluetooth environment poses unusualchallenges to AGC design, due to frequency hopping of the transmitterand the possibility of strong interfering signals at frequencies nearthe transmitter frequency. Because of the rapid variations in the signalthat may occur due to frequency hopping, the AGC circuit preferablygenerates an estimate of the level of the input signal received from thetransmitter over only an initial portion of the packet header at eachnew frequency. Interference at adjacent frequencies is filtered out ofthe AGC input, and sufficient dynamic range is provided in the inputcircuits of the receiver so that the amplitude of the input signal,following amplification, can be held approximately constant even in thepresence of interference. The amplification level of the input circuitsis preferably held constant over the entire duration of the packet,unless the AGC circuit detects a substantial change in the input signalamplitude.

[0017] Although preferred embodiments are described herein with specificreference to the Bluetooth standard and wireless GFSK receivers, theprinciples of the present invention may also be applied, mutatismutandis, to digital receivers and demodulators of other types. Whilethe methods and devices of the present invention are directedparticularly at solving problems inherent in wireless transmission, theprinciples embodied therein are also applicable to wireline receivers,especially in systems that use FSK modulation schemes.

[0018] There is therefore provided, in accordance with a preferredembodiment of the present invention, a method for synchronizing areceiver to a stream of transmitted symbols that includes a knownsynchronization word, the method including:

[0019] receiving a signal in which the symbols, including thesynchronization word, are encoded by frequency shift keying;

[0020] sampling and digitizing the signal to generate a sequence ofinput samples;

[0021] determining, for each of the input samples, a phase differencerelative to a preceding input sample in the sequence, thereby generatinga sequence of differential samples corresponding respectively to theinput samples; and

[0022] matching the differential samples to the synchronization word.

[0023] Preferably, receiving the signal includes receiving the signal ata radio frequency having a frequency offset relative to a channelfrequency designated for the signal, and determining the phasedifference includes canceling the frequency offset out of thedifferential samples before matching the differential samples to thesynchronization word.

[0024] In a preferred embodiment, receiving the signal includesreceiving the stream of symbols encoded by Gaussian frequency shiftkeying.

[0025] Preferably, the symbols are transmitted at a given symbol rate,and sampling and digitizing the signal includes generating the inputsamples at a sample rate greater than the symbol rate, whereindetermining the phase difference includes computing the phase differencebetween pairs of the input samples that are separated by an intervalthat is a reciprocal of the symbol rate.

[0026] Additionally or alternatively, determining the phase differenceincludes taking a complex cross product between each of the inputsamples and the preceding input sample.

[0027] In a preferred embodiment, matching the differential samplesincludes determining reference samples that correspond to frequencyshift keying of the synchronization word, and correlating the sequenceof differential samples with the reference samples. Preferably,determining the reference samples includes providing coefficients suchthat multiplication of the symbols in the synchronization word by thecoefficients will generate the reference samples, and correlating thesequence of differential samples includes multiplying the differentialsamples by the coefficients.

[0028] Additionally or alternatively, correlating the sequence ofdifferential samples includes computing a sequence of correlation valuesby correlating different, respective portions of the sequence of inputsamples with the synchronization word, and matching the differentialsamples includes choosing the portion of the sequence of input samplesthat best matches the synchronization word by finding a peak value amongthe correlation values corresponding to the chosen portion. Preferably,sampling and digitizing the signal includes generating complex samples,and computing the sequence of correlation values includes computingcomplex correlation values, wherein the method includes determining aphase angle of the peak correlation value, and correcting a phase of theinput samples of the signal subsequent to the synchronization wordresponsive to the phase angle.

[0029] Preferably, matching the differential samples includes finding atime offset of the input samples relative to the synchronization word,and the method includes decoding the input samples of the signalsubsequent to the synchronization word responsive to the time offset.Further preferably, matching the differential samples includes finding afrequency offset of the signal relative to an expected frequency, anddecoding the input samples includes adjusting the decoding of thesamples responsive to the frequency offset. Additionally oralternatively, decoding the input samples finding correlations betweenportions of the sequence of input samples and corresponding groups ofsymbols, so as to determine the symbols that were transmitted in thestream.

[0030] There is also provided, in accordance with a preferred embodimentof the present invention, a method for decoding a stream of transmittedsymbols, including:

[0031] receiving a signal in which the symbols are encoded by frequencyshift keying;

[0032] sampling and digitizing the signal to generate a sequence ofinput samples;

[0033] defining a plurality of hypotheses with respect to a selectedgroup of the symbols occurring in succession in the stream, each suchhypothesis including a different set of possible values of the symbolsin the group;

[0034] finding a respective level of correlation between each of theplurality of hypotheses and the input samples in a portion of thesequence corresponding to the selected group of the symbols;

[0035] choosing one of the hypotheses responsive to the level ofcorrelation thereof; and

[0036] for at least one of the symbols in the selected group,determining a decoded value of the symbol responsive to the value of thesymbol in the chosen hypothesis.

[0037] Preferably, finding the respective level of correlation includesdetermining reference samples that correspond to frequency shift keyingof the symbol values in each of the hypotheses, and correlating thesamples in the portion of the sequence with the reference samplesFurther preferably, determining the reference samples includes providingcoefficients such that multiplication of the symbol values in each ofthe hypotheses by the coefficients will generate the reference samples,and correlating the samples includes multiplying the samples by thecoefficients. More preferably, sampling and digitizing the signalincludes generating complex samples, and multiplying the samplesincludes rotating a phase of each of the complex samples responsive tothe coefficients. Most preferably, rotating the phase of each of thecomplex samples further includes rotating the phase so as to correct fora frequency offset of the signal relative to an expected frequency.

[0038] In a preferred embodiment, the symbols are transmitted at a givensymbol rate, and sampling and digitizing the signal includes generatingthe input samples at a sample rate greater than the symbol rate, anddetermining the reference samples includes determining the referencesamples at the sample rate.

[0039] Additionally or alternatively, outputting the decoded value ofthe symbol includes outputting the decoded value of a current symbol,and defining the plurality of hypotheses includes selecting the group ofthe symbols to include at least one symbol preceding the current symbolin the succession and at least one symbol following the current symbolin the succession. Preferably, the at least one symbol preceding thecurrent symbol includes three symbols preceding the current symbol, andthe at least one symbol following the current symbol includes threesymbols following the current symbol.

[0040] Further additionally or alternatively, selecting the group of thesymbols includes selecting the at least one symbol preceding the currentsymbol such that the decoded value of the at least one symbol precedingthe current symbol has already been determined, and defining theplurality of hypotheses includes using only the hypotheses that includethe determined value of the at least one symbol preceding the currentsymbol. Preferably, the method includes repeating the step of definingthe plurality of hypotheses with respect to the at least one symbolfollowing the current symbol, using only the hypotheses that include thedetermined value of the current symbol, and repeating with respect tothe at least one symbol following the current symbol the steps offinding the respective level of correlation, choosing one of thehypotheses, and determining the decoded value.

[0041] Preferably, choosing the one of the hypotheses includes computinga correlation between each of the plurality of hypotheses and the inputsamples, and choosing the one of the hypotheses that has a maximal valueof the correlation compared to the other hypotheses.

[0042] In a further preferred embodiment, sampling and digitizing thesignal includes generating complex samples of the signal, anddetermining the decoded value includes determining the decoded values ofsuccessive first and second ones of the symbols, and the method includescomparing a phase difference between a first one of the samples,corresponding to the first symbol, and a second one of the samples,corresponding to the second symbol, to a difference between the firstand second symbols so as to find a frequency offset of the signalrelative to an expected frequency. Preferably, finding the level of thecorrelation includes applying a phase rotation to the complex samplesresponsive to the frequency offset.

[0043] In yet another preferred embodiment, receiving the signalincludes receiving a packet of data transmitted from a transmitter to areceiver, the packet including an error correcting code and ending witha final symbol, such that there is an increased level of uncertainty inthe decoded value of the final symbol relative to the other symbols inthe packet, and the method includes performing an error check on thepacket at the receiver based on the code in a manner that is insensitiveto the decode value of the final symbol.

[0044] There is additionally provided, in accordance with a preferredembodiment of the present invention, a method for decoding a stream oftransmitted symbols, including:

[0045] receiving a signal including a packet of data symbols transmittedfrom a transmitter to a receiver, the packet ending with a final symbol;

[0046] sampling and digitizing the signal to generate a sequence ofinput samples;

[0047] adding to the samples at the receiver one or more tail samplescorresponding to a tail symbol following the final symbol in the packet;and

[0048] decoding the symbols by processing, for each of the symbols, acorresponding portion of the sequence of the samples, such that theportion corresponding to the final symbol includes at least one of thetail samples.

[0049] Preferably, adding the one or more tail samples includesidentifying one of the input samples as a final sample, derived from thefinal symbol, and duplicating the final sample.

[0050] Additionally or alternatively, when the packet includes a headerindicating a length of the packet, adding the one or more tail samplesincludes reading the length by decoding the header, and identifying thefinal symbol responsive to the length.

[0051] Preferably, decoding the symbols includes finding, for each ofthe symbols, a correlation between the corresponding portion of thesequence of the samples and a hypothesis including possible values of agroup of the symbols. Additionally or alternatively, decoding thesymbols includes processing the samples responsive to intersymbolinterference between the symbols in the received signal.

[0052] There is further provided, in accordance with a preferredembodiment of the present invention, a method for decoding a stream oftransmitted symbols, including:

[0053] receiving a signal at a transmission frequency, in which signalthe symbols are encoded;

[0054] sampling and digitizing the signal to generate a sequence ofcomplex input samples;

[0055] processing the samples so as to determine decoded values ofsuccessive first and second ones of the symbols;

[0056] computing a phase difference between a first one of the samples,corresponding to the first symbol, and a second one of the samples,corresponding to the second symbol; and

[0057] comparing the phase difference to a difference between the firstand second symbols so as to find a frequency offset of the transmissionfrequency relative to an expected frequency.

[0058] Preferably, computing the phase difference includes taking acomplex cross product between the first and second samples. Additionallyor alternatively, comparing the phase difference includes determiningreference samples that correspond to encoding of the first and secondsymbols, and taking a complex cross product between the referencesamples and the first and second samples.

[0059] Further additionally or alternatively, wherein processing thesamples includes computing a correlation between a hypothesis includingpossible values of a group of the symbols, including the first andsecond symbols, and a portion of the sequence of the samples includingthe first and second samples. Preferably, computing the correlationincludes computing a plurality of correlations with respect to differenthypotheses, and choosing the one of the hypotheses that has a maximalvalue of the correlation compared to the other hypotheses.

[0060] Preferably, the method includes applying a phase rotation,responsive to the frequency offset, to the complex samples subsequent tothe first and second samples in preparation for processing thesubsequent samples to determine the decoded values of the symbols towhich the subsequent samples correspond.

[0061] There is moreover provided, in accordance with a preferredembodiment of the present invention, a receiver, for receiving a streamof transmitted symbols that includes a known synchronization word, thereceiver including:

[0062] input circuitry, coupled to receive a signal in which thesymbols, including the synchronization word, are encoded by frequencyshift keying, and to sample and digitizing the signal to generate asequence of input samples; and

[0063] a synchronization word detector, coupled to receive the sequenceof input samples and adapted to determine, for each of the inputsamples, a phase difference relative to a preceding input sample in thesequence, thereby generating a sequence of differential samplescorresponding respectively to the input samples, and to detect thesynchronization word by matching the differential samples to thesynchronization word.

[0064] Preferably, the synchronization word detector includes at leastone multiplier, which is adapted to compute a complex cross productbetween each of the input samples and the preceding input sample.

[0065] Additionally or alternatively, the synchronization word detectoris adapted to determine reference samples that correspond to frequencyshift keying of the synchronization word, and includes a correlator,which is coupled to correlate the sequence of differential samples withthe reference samples. Preferably, the correlator is adapted to computea sequence of correlation values by correlating different, respectiveportions of the sequence of input samples with the synchronization word,and the synchronization word detector includes a peak detector, coupledto find a peak value among the correlation values of the differentportions, thus indicating the portion of the sequence of input samplesthat best matches the synchronization word.

[0066] In a preferred embodiment, the input circuitry is adapted togenerate complex samples, and the correlator is adapted to computecomplex correlation values, and the receiver includes an automaticfrequency control circuit, which is adapted to find a phase angle of thepeak correlation value, and a rotator, which is coupled to the automaticfrequency control circuit so as to correct a phase of the input samplesof the signal subsequent to the synchronization word responsive to thephase angle.

[0067] Preferably, the synchronization word detector is adapted to finda time offset of the input samples relative to the synchronization word,and the receiver includes a demodulator, which is coupled to receive thetime offset from the synchronization word detector and to decode theinput samples of the signal subsequent to the synchronization wordresponsive to the time offset.

[0068] There is furthermore provided, in accordance with a preferredembodiment of the present invention, a receiver for decoding a stream oftransmitted symbols, including:

[0069] input circuitry, coupled to receive a signal in which the symbolsare encoded by frequency shift keying, and to sample and digitize thesignal to generate a sequence of input samples; and

[0070] a demodulator, adapted to process a plurality of hypotheses withrespect to a selected group of the symbols occurring in succession inthe stream, each such hypothesis including a different set of possiblevalues of the symbols in the group, the demodulator including:

[0071] a correlator, adapted to find a respective level of correlationbetween each of the plurality of hypotheses and the input samples in aportion of the sequence corresponding to the selected group of thesymbols; and

[0072] a selector, adapted to choose one of the hypotheses responsive tothe level of correlation thereof, so as to determine, for at least oneof the symbols in the selected group, a decoded value of the symbolresponsive to the value of the symbol in the chosen hypothesis.

[0073] Preferably, the demodulator is operative to determine referencesamples that correspond to frequency shift keying of the symbol valuesin each of the hypotheses, and the correlator is coupled to correlatethe samples in the portion of the sequence with the reference samples.Further preferably, the demodulator is adapted to determine thereference samples by providing coefficients such that multiplication ofthe symbol values in each of the hypotheses by the coefficients willgenerate the reference samples, and the correlator includes at least onemultiplier, which is coupled to multiply the samples by thecoefficients. Most preferably, the input circuitry is adapted togenerate complex samples, and the at least one multiplier includes acomplex multiplier, which is coupled to rotate a phase of each of thecomplex samples responsive to the coefficients.

[0074] Preferably, the input circuitry is adapted to generate complexsamples of the signal, and the demodulator is operative to determine thedecoded values of successive first and second ones of the symbols, andthe receiver includes an automatic frequency control circuit, which iscoupled to compare a phase difference between a first one of thesamples, corresponding to the first symbol, and a second one of thesamples, corresponding to the second symbol, to a difference between thefirst and second symbols so as to find a frequency offset of the signalrelative to an expected frequency. Most preferably, the receiverincludes at least one rotator, which is coupled to apply a phaserotation to the complex samples responsive to the frequency offset.

[0075] In a preferred embodiment, the signal includes a packet of datatransmitted from a transmitter to a receiver, the packet including anerror correcting code and ending with a final symbol, such that there isan increased level of uncertainty in the decoded value of the finalsymbol relative to the other symbols in the packet, and including aprocessor, adapted to perform an error check on the packet at thereceiver based on the code in a manner that is insensitive to the decodevalue of the final symbol.

[0076] There is also provided, in accordance with a preferred embodimentof the present invention, a receiver for decoding a stream oftransmitted symbols, including:

[0077] input circuitry, coupled to receive a signal including a packetof data symbols transmitted from a transmitter to a receiver, the packetending with a final symbol, and to sample and digitize the signal togenerate a sequence of input samples; and

[0078] demodulation circuitry, which is adapted to add to the samplesone or more tail samples corresponding to a tail symbol following thefinal symbol in the packet, and to decode the symbols by processing, foreach of the symbols, a corresponding portion of the sequence of thesamples, such that the portion corresponding to the final symbolincludes at least one of the tail samples.

[0079] In a preferred embodiment, the packet includes a headerindicating a length of the packet, and the receiver includes aprocessor, which is adapted to read the length by decoding the header,so as to identify the final symbol responsive to the length.

[0080] There is additionally provided, in accordance with a preferredembodiment of the present invention, a receiver for decoding a stream oftransmitted symbols, including:

[0081] input circuitry, coupled to receive a signal at a transmissionfrequency, in which signal the symbols are encoded, and to sample anddigitize the signal to generate a sequence of complex input samples;

[0082] a demodulator, which is coupled to process the samples so as todetermine decoded values of successive first and second ones of thesymbols; and

[0083] an automatic frequency control circuit, which is adapted tocompute a phase difference between a first one of the samples,corresponding to the first symbol, and a second one of the samples,corresponding to the second symbol, and to compare the phase differenceto a difference between the first and second symbols so as to find afrequency offset of the transmission frequency relative to an expectedfrequency.

[0084] Preferably, the automatic frequency control circuit includes acomplex multiplier, which is coupled to take a complex cross productbetween the first and second samples so as to determine the phasedifference therebetween. Additionally or alternatively, the circuitincludes a complex multiplier, which is coupled to take a complex crossproduct between the reference samples and the first and second samplesso as to find the frequency offset.

[0085] Preferably, the receiver includes a rotator, which is coupled toapply a phase rotation, responsive to the frequency offset, to thecomplex samples subsequent to the first and second samples inpreparation for processing the subsequent samples to determine thedecoded values of the symbols to which the subsequent samplescorrespond.

[0086] The present invention will be more fully understood from thefollowing detailed description of the preferred embodiments thereof,taken together with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

[0087]FIG. 1 is a block diagram that schematically illustrates a digitalreceiver, in accordance with a preferred embodiment of the presentinvention;

[0088]FIG. 2 is a block diagram that schematically illustrates anautomatic gain control circuit, in accordance with a preferredembodiment of the present invention;

[0089]FIG. 3 is a block diagram that schematically illustrates a gainchange evaluation circuit used in the automatic gain control circuit ofFIG. 2, in accordance with a preferred embodiment of the presentinvention;

[0090]FIG. 4 is a block diagram that schematically illustrates a gainand command evaluation circuit used in the automatic gain controlcircuit of FIG. 2, in accordance with a preferred embodiment of thepresent invention;

[0091]FIG. 5 is a block diagram that schematically illustrates asynchronization word detector, as is known in the art;

[0092]FIG. 6 is a block diagram that schematically illustrates asynchronization word detector and automatic frequency control circuit,in accordance with a preferred embodiment of the present invention;

[0093]FIG. 7 is a block diagram showing details of the synchronizationword detector of FIG. 6, in accordance with a preferred embodiment ofthe present invention;

[0094]FIG. 8 is a block diagram that schematically illustrates acorrelator circuit used in the synchronization word detector of FIG. 6,in accordance with a preferred embodiment of the present invention;

[0095]FIG. 9 is a block diagram that schematically illustrates a samplerotator and demodulator circuit, in accordance with a preferredembodiment of the present invention;

[0096]FIG. 10 is a block diagram that schematically illustrates anautomatic frequency control circuit, in accordance with a preferredembodiment of the present invention;

[0097]FIG. 11A is a block diagram that schematically illustrates afrequency error detector used in the circuit of FIG. 10, in accordancewith a preferred embodiment of the present invention; and

[0098]FIG. 11B is a block diagram that schematically illustrates a loopfilter used in the circuit of FIG. 10, in accordance with a preferredembodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS System Overview

[0099]FIG. 1 is a block diagram that schematically illustrates areceiver 20, for use in a digital communications system, in accordancewith a preferred embodiment of the present invention. As described indetail hereinbelow, receiver 20 is designed to process and decode FSKsignals, particularly GFSK signals, as are used in the Bluetooth system.It receives signals over the air in the 2.4 GHz band and demodulates thesignals to output a bitstream of ones and zeroes. The bitstream ispassed to a media access control (MAC) processor (not shown in thisfigure), as specified by the Bluetooth standard. Although elements ofreceiver 20 are described herein with specific reference to Bluetooth,it will be appreciated that many of these elements are also applicableto data receivers of other types.

[0100] Radio frequency (RF) signals received by receiver 20 areamplified by a low-noise amplifier (LNA) 21 and are then down-convertedby a mixer 22 to generate I and Q intermediate frequency (IF) signals,preferably at a carrier frequency of 500 kHz. The I and Q signals areamplified by respective variable-gain amplifiers (VGAs) 23 and arelow-pass filtered by filters 24 to remove interference. Filters 24 areimportant particularly for removing interfering signals from otherfrequencies in the 2.4 GHz band, neighboring on the carrier frequency towhich receiver 20 is currently tuned. The Bluetooth standard requiresreceivers to function even in the presence of strong interference fromchannels 1-3 MHz away from the current receive frequency.

[0101] The I and Q signals are multiplexed by a multiplexer 25 through asingle sample/hold circuit 26. The samples are digitized by ananalog/digital converter 27 and are then separated by a demultiplexer 28to generate parallel streams of I and Q data, preferably comprising9-bit samples at 22 MHz. All further processing is performed digitally,unlike Bluetooth receivers known in the art.

[0102] The digital I and Q samples contain a residual DC offset. Theyare preferably converted to baseband samples by respective DC removalcircuits 30, which function simply by finding and subtracting theaverage levels from the sample streams. Following DC removal, the I andQ samples are still offset in time from their correct baseband valuesdue to the residual IF (500 kHz) carrier, and are also mutually offsetby 90°. A fast rotator 33 rotates the phases of the I and Q samples toremove the baseband offset.

[0103] An automatic gain control (AGC) circuit 32 estimates the level ofthe input signals based on the digitized, rotated samples, and uses theestimate to set the gain of LNA 21 and VGAs 23. The operation of AGCcircuit 32 is described in detail hereinbelow.

[0104] Following DC removal and rotation, interpolation and decimationblocks 34 interpolate the samples in order to realign them in time.These blocks also perform digital low-pass filtering to removeout-of-band noise and interference that was not suppressed by analoglow-pass filters 24. The output sample rate of blocks 34 is decimateddown to 4 Ms/s.

[0105] Each Bluetooth packet begins with a special header known as anaccess code, which is either 68 or 72 bits long and includes a 64-bitsync word. The sync word is known to the MAC processor, in accordancewith protocols specified by the Bluetooth standard. Other methods ofdigital communications use similar codes for receiver synchronization.Digital samples output by blocks 34 are input to a sync word detector(SWD) 36, which correlates the samples with the known sync word in orderto detect the start of a Bluetooth packet. Preferably, SWD 36 operatesonly on an initial portion of the sync word, most preferably on thefirst 33 bits. When the SWD detects the start of a packet, the result ispreferably confirmed by comparing a decision output of receiver 20 to atleast some of the remaining bits in the known sync word, most preferablythe last 19 bits. If the number of discrepancies between the decisionoutput and the remaining sync word bits is less than a predeterminedthreshold, which is typically set to two, receiver 20 determines that ithas received and synchronized itself to a packet. At this point, theoutput of AGC circuit 32 is frozen, and the subsequent demodulatedsymbols in the packet are passed to the MAC for further processing.

[0106] SWD 36 also passes the correlation results to an initialfrequency detector 38, which uses these results to make initialestimates of the time and frequency offsets to be used by receiver 20 indemodulating the samples. These estimates are used to initialize anautomatic frequency control (AFC) circuit 40 for each new packet.

[0107] The samples output by blocks 34 are also input to a buffer androtator circuit 42, which rotates the phase of the sample streams basedon instructions from AFC circuit 40. The rotated samples are passed to ademodulator 44, which uses a correlator engine to performpartially-coherent symbol detection. This approach, which is describedin detail hereinbelow, uses the intersymbol interference that isinherent in the GFSK scheme to improve the performance of thedemodulator. A bank of correlators is used to decide on the likeliestestimate for the current symbol, which is then output to the MACprocessor. The I and Q values belonging to the “winning” correlator areinput to AFC circuit 40, in order to update the frequency estimate. Thisupdated value is in turn used to adjust the phase input to the rotatorsin circuit 42.

[0108] In operation, receiver 20 can be in any one of four possiblestates:

[0109] Idle-Receiver 20 is typically associated with a transmitter (notshown) in a single chip or unit. While the transmitter is transmittingdata, the associated receiver at the transmitting end of the link isshut down.

[0110] Acquiring-In this mode, the receiver is waiting for data, anddemodulator 44, along with other elements of the receiver that are notneeded for sync word acquisition, is shut down until the beginning of adata packet is detected. Sync word detector 36 tries to match theincoming samples to the sync word and estimates values of channelattenuation, timing and frequency offset.

[0111] Confirming-Once sync word detector 36 has found a match that isbetter than a given threshold between the sample stream and the syncword, the receiver processes and demodulates the remainder of the syncword. In this phase, the entire receiver is active. The AGC and AFCcircuits may continue to track and adjust for any varying channelparameters.

[0112] Demodulating-When it is confirmed that a packet has beendetected, demodulator 44 continues processing the remaining data in thepacket and passes the decoded symbols to the MAC layer. Preferably, AGCcircuit 32 is frozen. At the end of the packet, the receiver returns toidle mode.

Automatic Gain Control

[0113]FIG. 2 is a block diagram showing details of AGC circuit 32, inaccordance with a preferred embodiment of the present invention. Thiscircuit is designed to determine the level of the current signal withina short time after beginning to receive a packet at receiver 20, mostpreferably within the time it takes to receive ten symbols (i.e., 10 μsat the Bluetooth rate of 1 Ms/s). It then controls LNA 21 and VGAs 23 soas to bring the average signal level in the frequency channel ofinterest into a predetermined amplitude window, preferably within 3 dBof a given reference level. The AGC circuit must also be resistant tointerference from neighboring channels, so that a substantially constantamplitude level is maintained in the current frequency channel,regardless of the interference level.

[0114] As seen in FIG. 2, a gain change evaluation block 50 receives Iand Q samples of the input signal and, on the basis of these samples,outputs a limited gain change value. An adder 52 sums this value withthe previous value of the gain, provided by a feedback circuit 58, togive the total gain that is to be applied. A gain and command evaluationblock 54 determines the commands that are to be sent to the LNA and VGAsin order to obtain the desired gain levels. An adder 56 sums the LNA andVGA gains to provide the total gain to feedback circuit 58.

[0115] The total gain is also used to drive gain control logic 60, whichgenerates the receive signal strength indicator (RSSI) and energy detect(ED) indicator, as required by the Bluetooth specification. The RSSI ispreferably given (in dBm) by the difference between the reference pointpower of A/D converter 27 and the total gain, and is used to control theoutput power level of the transmitter (not shown). The ED indicator isset high as long as the total gain is below a preset threshold,indicating that a Bluetooth signal is present at the receiver.

[0116]FIG. 3 is a block diagram showing details of gain changeevaluation block 50, in accordance with a preferred embodiment of thepresent invention. Input I and Q samples received from rotator 33 arefiltered by low-pass filters 68, which preferably operate at a samplefrequency of 22 MHz and have a controllable cutoff frequency, which istypically set in the range 0.5-1 MHz. A signal level estimator 70computes the energy value I²+Q² based on the low-pass filtered samples.Filtering the samples before signal level estimation reduces thelikelihood that the AGC circuit will lock onto transient interference,rather than the signal itself. An accumulator 72 generates an averageenergy value by summing the sample energies over a predeterminedintegration period, which may be adjusted by setting an appropriateregister value. The average energy value is truncated and limited, by alimiter 74, preferably to an eight-bit value.

[0117] The limited energy from limiter 74 is used as an index to alook-up table (LUT) 76, which reads out an appropriate gain value. Thegain is preferably logarithmic in the input energy values. A subtractor84 takes a difference between the gain value and a programmablesteady-state gain value, which is stored in a setpoint register and isread out through a multiplexer 82. When the energy reaches its upperlimit (255), however, as determined by a comparator 78, and a setpointflag is set at an input to an AND gate 80, multiplexer 82 is driven tooutput a zero to adder 84. This situation immediately causes the gain ofthe analog amplifiers to drop down by a large jump, typically 12 dB, inorder to prevent saturation of the receiver input.

[0118] An absolute value block 86 calculates the absolute value of thegain change that is output by adder 84. A comparator 88 compares theabsolute gain change to a programmable gain step threshold. If thechange is over the threshold, a multiplexer 90 outputs the limited gainchange that has been determined by block 50. Otherwise, no gain changeis invoked.

[0119]FIG. 4 is a block diagram showing details of gain and commandevaluation block 54, in accordance with a preferred embodiment of thepresent invention. As noted above, this block receives the total gainvalue that is generated by adder 52. The total gain is limited,preferably to an eight-bit value, by a limiter 100 and is then passed toa hysteresis circuit 102, which generates a gain command to LNA 21.Typically, the LNA has a fixed gain of about 7 dB. If the LNA gain isturned on, the hysteresis circuit keeps it on until the total gain dropsbelow 7 dB (or whatever other fixed gain level the LNA is set for). Whenthe LNA is turned off, the hysteresis circuit keeps it off until thetotal gain reaches the upper limit of the gain of VGAs 23, typicallyabout 45 dB. Thus, the LNA gain command is typically a simple on/offcommand issued by circuit 102.

[0120] To determine the gain to be applied by VGAs 23, an adder 106subtracts the current LNA gain from the limited total gain that isoutput by limiter 100. The current LNA gain (when the LNA gain is turnedon) is read from a LNA gain register through a multiplexer 104. The VGAgain is divided by a preset gain step, using a multiplier 108 followedby truncation, and is then rounded, preferably to a four-bit value, by arounder 110. This four-bit value is the gain command, which is providedto the VGAs in order to set the VGA gain level. Multiplying the gaincommand by the gain step, using a multiplier 112, gives the actual VGAgain.

Sync Word Detection

[0121]FIG. 5 is a block diagram that schematically illustrates a syncword detector (SWD) 120, as is used in digital receivers known in theart. SWD 120 receives a sequence of digital samples X_(t)=(x_(t−N+1), .. . , x_(t)) from a filter 122, such as the digital filter that is usedto implement interpolation and decimation block 34 (FIG. 1). The SWDalso receives the expected access code of the incoming data packet froma MAC processor 124. A GFSK modulator 126 takes a selected subset of thebits in the access code, AC′=(b_(k), . . . , b_(n)), and modulates thebits to create a sequence of expected “ideal” samples, or referencesamples, SW=GESK(AC′)=(s₁, . . . s_(N)). A correlator 126 correlatesthese ideal samples with the actual samples coming from the filter togenerate a correlation function: $\begin{matrix}{{P(t)} = {{{SW} \cdot X_{t}^{*}} = {\sum\limits_{k = 1}^{N}{s_{k}x_{t - N + k}^{*}}}}} & (1)\end{matrix}$

[0122] A peak detector 130 finds the maximum of the correlationfunction, which indicates the “correct” match between the actual signaland the access code. SWD 120 passes the match to a demodulator 132,which uses the timing determined by the SWD to decode the samples.

[0123] Unfortunately, this method does not work well if there is aninitial frequency offset between the input signal and the “ideal” signalgenerated by GFSK modulator 126. If the sampling frequency is F_(s), andthe frequency offset is f, then the received signal (ignoring theeffects of noise) is {tilde over (x)}_(n)=x_(n)·e^(j(kf*n)) wherein$k = {2 \cdot \pi \cdot {\frac{f}{Fs}.}}$

[0124] The Bluetooth standard allows the transmitted initial centerfrequency to deviate by ±75 kHz. The difference between the phase of theideal signal and the signal with frequency drift of 75 kHz is thereforealmost 180° after 6 bits. Under these conditions, a matched filteringapproach as embodied in SWD 120 will not work.

[0125]FIG. 6 is a block diagram that schematically illustrates SWD 36,as used in receiver 20 (FIG. 1), in accordance with a preferredembodiment of the present invention. To overcome the problem offrequency offset, SWD 36 comprises a differential block 142, whichcomputes the frequency difference of each sample with respect to apreceding sample, Δ clocks earlier. In practice, the frequencydifference is preferably found by taking a complex cross product of thesamples, i.e., multiplying each sample by the complex conjugate of thecorresponding earlier sample, to generate a differential sampley_(k):=x_(k)·x_(k−Δ) ^(*). In the present embodiment, with a sample ratefour times the symbol rate, we set Δ=4.

[0126] By the same token, a GFSK modulator and differential block 140generates differential reference samples c_(k):=s_(k)·s_(k−Δ) ^(*),wherein the s_(k) are the original “ideal” samples (without noise orfrequency offset) based on the sync word. Even if the signal frequencyis now assumed to have an offset f relative to the ideal frequency, theresultant drift is canceled by the difference (cross product)operations. For each possible value of a delay time t, a correlator 144generates the result: $\begin{matrix}{{P(t)} = {{\sum\limits_{k^{\prime} = 1}^{N}{c_{k} \cdot y_{t - N + k}^{*}}} = {{R\left( {t - D} \right)} \cdot ^{j\quad {({2\pi \quad {fT}})}}}}} & (2)\end{matrix}$

[0127] wherein R(t−D) is the self-correlation of the sequence ofdifferential samples (taken over the N samples), D is the unknownchannel delay, and T is the symbol period. Since the self-correlation ofthe amplitude is independent of the frequency offset, correlator 144 cancompare the samples to the access code over a large number of symbols,thus improving the accuracy of matching between the samples and the syncword.

[0128] A peak detector 146 finds the peak correlation P_(max) among thecorrelation values that were found for different values of t. The peakcorrelation will occur for the value of t that is closest to the actualchannel delay D. Preferably, the peak detector finds the maximum of thereal (I) part of the correlation values, since the maximum allowedfrequency offset, f, is relatively small. The peak detector searchesover the calculated values of I until a value is found that exceeds apreset threshold. Alternatively, other measures of peak correlation maybe used, such as a sum of squares of the real and imaginary parts of thecorrelation, a weighted sum of the absolute values of the real andimaginary parts, a maximum of the absolute values real and imaginaryparts, or some other combination of the real and imaginary parts, forexample max(|I|, |Q|)+½min(|I|, |Q|). Other possibilities will beapparent to those skilled in the art. Once the preset threshold ispassed, the peak detector continues searching until it finds the localmaximum in P(t). Preferably, after finding the local maximum, the peakdetector continues search for a certain additional length of time, toensure that there is not a higher maximum subsequent to the localmaximum. The value of t that gives the peak correlation value is used tostart demodulator 44.

[0129] The phase of the peak correlation, e^(j(2πfT)), is used todetermine the initial frequency offset f. For this purpose, the real (I)and imaginary (Q) parts of the peak correlation are passed to AFCcircuit 40, which uses these values to determine an initial phasecorrection for application by rotator 42.

[0130]FIG. 7 is a block diagram that schematically illustrates detailsof an implementation of SWD 36, in accordance with a preferredembodiment of the present invention. The figure shows the resolution (inbits) of digital signals used in the SWD by way of example, and notlimitation. Those skilled in the art will be capable of adjusting theseresolution parameters to meet different system requirements.Differential block 142 comprises a four-sample delay line 150 and amultiplier 152, which multiplies each sample by the complex conjugate ofthe delayed sample four clocks earlier. Preferably, the samples areinput to the multiplier at 10-bit resolution. The 21-bit product isshifted right, preferably by eight bits, by a shifter 154 and is thenpreferably truncated to 10 bits.

[0131] GFSK modulator and differential block 140 is preferablyimplemented as a table of “ideal” differential reference samples. Thetable accepts as input sequences of m bits {b_(i), . . . , b_(i+m−1)}from the sync word of the access code provided by MAC processor 124. Thetable outputs the complex differential samples c_(k) described above,based on the samples s_(k) generated by Gaussian modulation of the inputbits. For each successive input bit, m+1 new samples c_(k) are output,based on the m input bits up to and including the current bit. The widthof the table depends on the number of input bits, m, used to generateeach Gaussian sample. The inventors have found that m=3 gives goodresults. Alternatively, other values of m, such as m=5 or m=7, may beused, with or without Gaussian smoothing.

[0132] Using a linear approximation to compute the values of s_(k)(without Gaussian smoothing) gives the following table: TABLE I GFSKMODULATOR DIFFERENTIAL OUTPUT Sync word Samples c_(k)(I,Q) bits 0 1 2 3000 75 −103 75 −103 75 −103 75 −103 001 75 −103 75 −103 114 −58 127 0010 114 58 75 103 114 58 127 0 011 114 58 75 103 75 103 75 103 100 114−58 75 −103 75 −103 75 −103 101 114 −58 75 −103 114 −58 127 0 110 75 10375 103 114 58 127 0 111 75 103 75 103 75 103 75 103

[0133] In the table above, there are only three different complexcoefficients: TABLE II GFSK LUT COEFFICIENTS d₀ d₁ d₂ I 75 114 127 Q 10358 0

[0134] Alternatively, sets of five or seven coefficients may begenerated and used in like manner.

[0135] Returning now to FIG. 7, the actual and reference samples aremultiplied together by a multiplier 156. The product is thenright-shifted by a shifter 158, and summed by an adder 160 into anaccumulator 162, preferably at 20-bit resolution. By operating in thismanner over multiple samples, multiplier 156, adder 160 and accumulator162 compute a correlation between the samples and the given sync wordfor a selected timing relationship between the sample stream and theaccess code. The correlation is recomputed for each of a large number ofdifferent timing relationships. The correlation values are right-shiftedagain by a shifter 164 and are input to peak detector 146, preferably at13-bit resolution, in order to find the timing relationship that givesthe highest correlation value.

[0136]FIG. 8 is a block diagram that schematically shows details ofcorrelator 144, in accordance with a preferred embodiment of the presentinvention. This implementation actually combines the function of thecorrelator with GFSK modulator and differential block 140, renderingblock 140 functionally superfluous in this case. Here, correlator 144takes as input a portion of the sync word, which is stored in a syncword register 152, and a sliding window of 132 complex differentialsamples of the actual signal, y_(k), stored in a sample register 150.The inventors have found that taking 35 bits of the sync word, andcorrelating the resultant 132 differential reference samples with 132actual differential samples of the signal gives good results.Alternatively, larger or smaller numbers of sync word bits and ofdifferential samples may be used for this purpose.

[0137] The present implementation is based on the realization, asexplained above and shown in Tables I and II, that only five differentcoefficients—d₀, d₀*, d₁, d₁* and d₂—are needed in order to compute allpossible values of c_(k) for each successive group of three input bits.Four of these coefficients are mutually conjugant. For any givensequence of differential samples y_(k), the correlation P(t) between thesamples and the selected portion of the sync word is given by:$\begin{matrix}\begin{matrix}{{{P(t)} = \quad {\sum\limits_{k = 1}^{N}{c_{k} \cdot y_{t - N + k}^{*}}}}\quad} \\{= \quad {{d_{0} \cdot {\sum\limits_{j0}y_{t - N + {j0}}^{*}}} + {d_{0}^{*} \cdot {\sum\limits_{l0}y_{t - N + {l0}}^{*}}} + {d_{1} \cdot {\sum\limits_{j1}y_{t - N + {j1}}^{*}}} +}} \\{\quad {{d_{1}^{*} \cdot {\sum\limits_{l1}y_{t - N + {l1}}^{*}}} + {d_{2} \cdot {\sum\limits_{k1}y_{t - N + {k1}}^{*}}}}}\end{matrix} & (3)\end{matrix}$

[0138] In other words, P(t) is computed by taking appropriate partialsums of the sample values in register 150, and then multiplying thepartial sums by the appropriate coefficients. The actual sample valuesthat are to go into each partial sum are chosen by selectors 154, basedon the values of the sync word bits that correspond to the ideal sampleswith which the actual sample values are to be correlated. Each selectorreceives a successive group of three sync word bits and selects thesample values from a group of four differential samples corresponding tothese three bits.

[0139] The partial sums are computed by adders 162 in threeaccumulate/multiply blocks 156, 158 and 160. A complex multiplier 164 ineach of the blocks receives the partial sums and multiplies them (withconjugation as required) by the appropriate coefficient for each ofblocks 156, 158 and 160, i.e., by d₀, d₁ or d₃, respectively. Blocks 156and 158 each comprise two adders, in order to compute the separatepartial sums for multiplication by the coefficient and by its complexconjugate. The outputs of blocks 156, 158 and 160 are summed by an adder166 to give the correlation value P(t).

[0140] The selection function performed by selectors 154 is given by thefollowing table: TABLE III PARTIAL SUM SELECTION Bits (b₀, b₁, Outputsb₂) d₀ d₀* d₁ d₁* d₂ 000 y₀ + y₁ + 0 0 0 0 y₂ + y₃ 001 y₀ + y₁ 0 y₂ 0 y₃010 0 y₁ 0 y₀ + y₂ y₃ 011 0 y₁ + y₂ + 0 y₀ 0 y₃ 100 y₁ + y₂ + 0 y₀ 0 0y₃ 101 y₁ 0 y₀ + y₂ 0 y₃ 110 0 y₀ + y₁ 0 y₂ y₃ 111 0 y₀ + y₁ + 0 0 0y₂ + y₃

[0141] While this table refers only to the first group of three bits inthe sync word and to the first four corresponding samples of the signal,the identical selection function is performed for each subsequent groupof bits (b_(i), b_(i+1), b_(i+2)) and the corresponding group of samples(y_(4i), y_(4i+1), y_(4i+2), y_(4i+3)).

[0142] In an alternative embodiment of the present invention, not shownin the figures, the correlator stores the partial sums of products ofmultiplication of the actual differential samples y_(k) with the idealdifferential samples c_(k), instead of storing the differential samplesthemselves (as in register 150). The partial sums S_(t,n) are computedrecursively, based on the formula: $\begin{matrix}{S_{{t + 1},n} = {{\sum\limits_{k = 1}^{n}{c_{k} \cdot y_{t - N + k}^{*}}} = {S_{t,{n - 1}} + {c_{n} \cdot y_{t + 1}^{*}}}}} & (4)\end{matrix}$

[0143] Here n is the number of terms in the partial sum at each stage ofthe recursion, and N is the total number of terms in the fullcorrelation, S_(t,N).

[0144] The partial sums are used in calculating the full correlationvalues P(t). Preferably, the partial sums are held in shift registers.At each cycle of a counter, the registers are shifted, and theappropriate elements are selected and summed. When the counter reacheszero, a complete correlation value P(t) for the current value of t isread out. Appropriate logic designs for realizing such embodiments willbe apparent to those skilled in the art.

Demodulation Block

[0145] Demodulator 44 (FIG. 1) is based on finding the correlationP_(i)(t) of the N most recent actual samples with N correspondingreference samples: $\begin{matrix}{{P_{i}(t)} = {{S_{i} \cdot X_{t}^{*}} = {\sum\limits_{k = 1}^{N}{s_{i,k}x_{t - N + k}^{*}}}}} & (6)\end{matrix}$

[0146] Here X_(t) is a vector of the N most recent samples, and S_(i) isa vector of N ideal samples, corresponding to the ith hypothesis. Thepresent embodiment uses a sliding “window” of seven symbols, againstwhich the N samples are correlated. The window contains three previousbits ABC, one current bit x, and three future bits abc. One bit isdecoded in each cycle of the demodulator. Thus, at the cycle at whichthe current bit is to be decoded, the three previous bits ABC havealready been decoded in previous cycles. This leaves 16=2∝hypotheses forthe possible values of x and abc. If ABC=“001,” for example, thenpossible hypotheses are:

[0147] 001-0-000

[0148] 001-0-001

[0149] ...

[0150] 001-1-110

[0151] 001-1-111.

[0152] Alternatively, other windows may be used, which are wider ornarrower than seven bits, and/or which are shifted relative to thecurrent bit x. For example, the window may comprise four bits before xand two bits after, or five bits before x and one bit after. A drawbackof these shifted-window embodiments, however, is that they increase thesensitivity of demodulator 44 to frequency offset that was notaccurately corrected. In a further alternative embodiment, thedemodulator operates twice on each sample window: once to assignlikelihood weights to different possible values of the bits beingdecoded, and then a second time to determine the actual decision outputbased on the weights.

[0153] For each possible hypothesis (assumed in the description thatfollows to be of the form ABC-x-abc), the corresponding seven bits arepassed through a GFSK modulator. Using four samples per bit, we obtainN=28 complex reference samples (s₁. . . s₂₈). Alternatively, the numberof samples may be reduced in order to economize on logic complexity.Demodulator 44 computes the correlation of these reference samples withthe 28 actual samples being processed. The hypothesis that gives themaximal value of |P_(i)| defines the value of bit x. In the next cycle,this value becomes bit C, and the procedure is repeated. Typically, byincreasing the number of bits used in calculating the correlation, thebit error rate (BER) of the demodulator can be reduced, but with anattendant cost in terms of increased hardware requirements. Thus, inalternative embodiments of the present invention, not shown in thefigures, larger or smaller numbers of successive bits (or symbols) maybe used in demodulating the sample stream.

[0154]FIG. 9 is a block diagram that schematically shows details ofbuffer and rotator circuit 42 and of demodulator 44, in accordance witha preferred embodiment of the present invention. A sample buffer 200receives complex samples from filter 34. For each of the seven bits inthe current correlation window, selection logic in buffer 200 choosesthe appropriate four samples to be output from the buffer to demodulator44. Clocking of the samples is controlled by a cycle counter 206, whichis initialized by sync word detector (SWD) 36 upon detection of the syncword, as described above. Preferably, the samples enter buffer 200 at 4Ms/s, while counter 206 clocks the samples out at a substantially higherrate, most preferably 44 Ms/s, so that the correlation values for all ofthe different hypotheses can be computed in one period of the symbolclock (1 μs). The counter thus cycles from 0 to 43 for each symbol thatthe demodulator processes, and outputs the current bit value x when thecycle reaches zero.

[0155] Preferably, MAC processor 124 determines the number of symbols inthe payload of the current packet by reading the data length field inthe packet header. This packet header is in an initial part of thedecision bitstream that the MAC processor receives from demodulator 44.Based on the packet length, MAC processor 124 determines the time atwhich the last bit of the packet is received, and thus the time at whichthe last valid sample enters buffer 200. The processor then actuates a“sample hold” signal, which instructs buffer 200 not to receive any moresamples from filter 34, but rather to hold, or duplicate, the lastsample received. Holding the last sample in this manner prevents theintroduction of noise into demodulator 44, which may otherwise occur dueto the abrupt drop in transmitted power after the last bit. As notedabove, the Bluetooth standard does not require any tail bits at the endof the data payload in the packet. The sample hold signal provided bythe MAC processor enables demodulator 44 to sustain a low bit error rate(BER) even on the final bits of the packet.

[0156] In an alternative embodiment, this “sample hold” technique is notused, and bit errors are tolerated at the end of the packet. When thepacket ends with an error detection code, such as a cyclic redundancycheck (CRC) code, however, it is still necessary to prevent CRC errors,which can cause the entire packet to be discarded. Therefore, when MACprocessor 124 performs the CRC check, the last bit or bits in the packet(which typically belong to the CRC code) are allowed to take on eitherof the values zero and one. In other words, the MAC processor performstwo or more alternative error checks, corresponding to the alternativeending bits of the packet. As long as one of the checks returns apositive result, the packet is considered to be valid. The concomitantloss in error checking confidence is not generally significant.

[0157] Returning now to FIG. 9, samples output from buffer 200 arerotated in phase by a rotator bank 204. The phase rotation is preferablyused both to correct for small frequency deviations and to carry out thecomplex multiplications that are a part of the correlation computationmade by a correlator 210, following the rotators. Bank 204 receives aphase correction from AFC circuit 40, preferably once per symbol (i.e.,at 1 MHz) An additional phase rotation signal is provided by a phasegeneration block 208, at the rate of counter 206. Block 208 generatesthe phase rotation signal based on the values of the three precedingbits (ABC) decoded by demodulator 44. These values are passed to block208 by an ABC update block 216, which preferably comprises a three-bitshift register.

[0158] The rotated samples are input from rotator bank 204 to aninternal buffer 209 at the rate of counter 206. Buffer 200 is needed inorder to store the samples, before rotation, until SWD 36 finds a matchbetween the signal and the known sync word. Only after the match is madecan AFC circuit 40 estimate the initial frequency offset and provide theproper correction to rotator bank 204. Buffer 209 holds the samplesafter rotation, for use by a correlator 210 in determining the values ofbits x-abc. The correlator accumulates the products of multiplicationthe reference samples and actual samples for each of the sixteendifferent hypotheses, as described above, so as to generate acorrelation value for each hypothesis.

[0159] After all of the 28 samples have been processed in this manner,correlator 210 holds the complex correlation results for each of thesixteen different ABCxabc hypotheses. A decision block 212 computes themagnitude of each result, in the form I²+Q² (wherein I and Q are thereal and imaginary parts of the correlation P_(i)). The result with thelargest magnitude is chosen as the “winner.” The decision output ispassed to AFC circuit 40 for use in determining the phase for rotationof the next symbol, as described below. The cross product between twosuccessive (I,Q) values corresponds to the phase shift due to thefrequency offset over a single symbol interval.

Automatic Frequency Control

[0160]FIG. 10 is a block diagram that schematically shows details of AFCcircuit 40, in accordance with a preferred embodiment of the presentinvention. A frequency error detector 250 begins operation as soon assync word detector 36 detects the sync word. The sync word detectorprovides detector 250 with the I_peak and Q_peak values generated bypeak detector 146 (FIG. 6). Frequency error detector 250 uses thesevalues to estimate the phase change f₀ in the signal over an interval of1 μs, resulting from the frequency offset of the input signal toreceiver 20, based on the following formula:

f ₀=tan⁻¹(Q _(—) peak/I _(—) peak)/4  (7)

[0161] The factor ¼ is used to account for the fact that there are foursamples per output symbol. This estimate of f₀ is used to rotate thefirst 28 samples that are read from buffer 200 into rotator bank 204(FIG. 9).

[0162] The AFC circuit then starts its regular operating loop. Therotated filter samples from rotator bank 204 are fed to detector 250,together with the corresponding decision bits from demodulator 44. Thedetector processes the samples, as described hereinbelow, to generate afrequency error signal Δf. The error signal is passed through a loopfilter 252 to generate a phase correction θ, which controls therotators. As the rotated samples are passed to detector 250 at a rate of4 Ms/s, while the decision bits are available at 1 Ms/s, AFC circuit 40preferably operates at 4 MHz.

[0163]FIG. 11A is a block diagram that schematically shows details offrequency error detector 250, in accordance with a preferred embodimentof the present invention. For each decision output set ABCxabc, detector250 receives from buffer 200 the samples corresponding to the oldestdata bits, B and A. Samples s(n−20), . . . , s(n−23) correspond to B,while samples s(n−24), . . . , s(n−27) correspond to A, as illustratedin the following table: TABLE IV SAMPLE BUFFER Output bit Samples a S(n)S(n-1) S(n-2) S(n-3) b S(n-4) . . . c . . . . . . x C B S(n-20) S(n-21)S(n-22) S(n-23) A S(n-24) S(n-25) S(n-26) S(n-23)

[0164] A difference block 256 takes the product of each of the sampless(n−20) to s(n−23), corresponding to B, with the complex conjugate ofthe corresponding sample for C (i.e., the complex cross product of thesamples) in order to find the phase change over one symbol period. Thisphase change reflects both the desired change in the phase of thesignal, θ_(n,k), due to the frequency modulation of the signal, and theundesired frequency drift per sample, Δf. Here n refers to the nth bitdecoded by demodulator 44, while k indexes the four samples (k=0, . . ., 3) corresponding to the decision bit. The output of difference block256 thus has the form:

S _(n,k*) S* _(n−1,k) =||S _(n,k) ||||S _(n−1,k)||exp{j(2πΔf·4+θ_(n,k)−θ_(n−1,k))}  (8)

[0165] for each of the values of k.

[0166] In order to separate the value of Δf from θ_(n,k), adiscriminator 258 multiplies the output of difference block 256 by thecross product of reference samples with unit amplitude corresponding tobits B and C, provided by a look-up table 257. This cross product isequal to exp{−j(θ_(n,k)−θ_(n−1,k))} so that the resulting frequencyerror output by discriminator 258 is simply||S_(n,k)||||S_(n−1,k)||exp{j(2πΔf·4). An offset detector 260 determinesthe value of Δf by taking the arctangent of the imaginary and real partsof the error output, Q_err/I_err. This value is provided to loop filter252 after every sample.

[0167]FIG. 11B is a block diagram that schematically shows details ofloop filter 252, in accordance with a preferred embodiment of thepresent invention. The loop filter preferably comprises a second-orderloop, which generates a rotation phase output θ_(n) to rotator bank 204based on the following equations:

θ_(n+1)=θ_(n) +f _(n)

f _(n+1) =f _(n) +r _(n) +K ₁ ·e _(n)  (9)

r _(n+1) =r _(n) +K ₂ ·e _(n)

[0168] Here e_(n) is the value of Δf that is output by frequency errordetector 250. K₁ and K₂ are constants, which are preferably setrespectively to be equal to 2⁻⁶ and 2⁻¹². Alternatively,, other valuesmay be chosen depending on the desired convergence characteristics ofthe filter, and K₂ may be set to zero if a first-order loop is desired.

[0169] Equations (9) are implemented in filter 252 using multipliers 262and 266 to apply K₂ and K₁, respectively. A Doppler rate accumulator 264calculates the rate r; a Doppler accumulator 268 calculates frequency f;and a phase accumulator 270 determines the final phase output θ. Dopplerrate accumulator 264 is preferably a saturating accumulator, which isinitialized to zero and is set to saturate at a value higher than themaximum frequency rate value. Doppler accumulator 268, which serves asthe frequency accumulator, is preferably also a saturating accumulator,which is set to saturate at a value higher than the maximum frequencyerror value. Accumulator 268 is set initially to a frequency errorestimate based on the peak I and Q values derived from SWD 36, asdescribed above. Phase accumulator 270 is preferably a wrappingaccumulator, which is set initially to zero and has a range (−π, π).

[0170] Although receiver 20 and elements within the receiver aredescribed herein with specific reference to the Bluetooth standard andprocessing of GFSK signals, the principles embodied in the receiver mayalso be applied, mutatis mutandis, to digital receivers and demodulatorsof other types, as well, particularly receivers and modems based oncontinuous-phase modulation (CPM) schemes, whether designed for wirelessor wireline operation. It will thus be appreciated that the preferredembodiments described above are cited by way of example, and that thepresent invention is not limited to what has been particularly shown anddescribed hereinabove. Rather, the scope of the present inventionincludes both combinations and subcombinations of the various featuresdescribed hereinabove, as well as variations and modifications thereofwhich would occur to persons skilled in the art upon reading theforegoing description and which are not disclosed in the prior art.

1. A method for synchronizing a receiver to a stream of transmittedsymbols that includes a known synchronization word, the methodcomprising: receiving a signal in which the symbols, including thesynchronization word, are encoded by frequency shift keying; samplingand digitizing the signal to generate a sequence of input samples;determining, for each of the input samples, a phase difference relativeto a preceding input sample in the sequence, thereby generating asequence of differential samples corresponding respectively to the inputsamples; and matching the differential samples to the synchronizationword.
 2. A method according to claim 1, wherein receiving the signalcomprises receiving the signal at a radio frequency having a frequencyoffset relative to a channel frequency designated for the signal, andwherein determining the phase difference comprises canceling thefrequency offset out of the differential samples before matching thedifferential samples to the synchronization word.
 3. A method accordingto claim 1, wherein receiving the signal comprises receiving the streamof symbols encoded by Gaussian frequency shift keying.
 4. A methodaccording to claim 1, wherein the symbols are transmitted at a givensymbol rate, and wherein sampling and digitizing the signal comprisesgenerating the input samples at a sample rate greater than the symbolrate, and wherein determining the phase difference comprises computingthe phase difference between pairs of the input samples that areseparated by an interval that is a reciprocal of the symbol rate.
 5. Amethod according to claim 1, wherein determining the phase differencecomprises taking a complex cross product between each of the inputsamples and the preceding input sample.
 6. A method according to claim1, wherein matching the differential samples comprises determiningreference samples that correspond to frequency shift keying of thesynchronization word, and correlating the sequence of differentialsamples with the reference samples.
 7. A method according to claim 6,wherein determining the reference samples comprises providingcoefficients such that multiplication of the symbols in thesynchronization word by the coefficients will generate the referencesamples, and wherein correlating the sequence of differential samplescomprises multiplying the differential samples by the coefficients.
 8. Amethod according to claim 6, wherein correlating the sequence ofdifferential samples comprises computing a sequence of correlationvalues by correlating different, respective portions of the sequence ofinput samples with the synchronization word, and wherein matching thedifferential samples comprises choosing the portion of the sequence ofinput samples that best matches the synchronization word by finding apeak value among the correlation values corresponding to the chosenportion.
 9. A method according to claim 8, wherein sampling anddigitizing the signal comprises generating complex samples, and whereincomputing the sequence of correlation values comprises computing complexcorrelation values, and comprising determining a phase angle of the peakcorrelation value, and correcting a phase of the input samples of thesignal subsequent to the synchronization word responsive to the phaseangle.
 10. A method according to claim 1, wherein matching thedifferential samples comprises finding a time offset of the inputsamples relative to the synchronization word, and comprising decodingthe input samples of the signal subsequent to the synchronization wordresponsive to the time offset.
 11. A method according to claim 10,wherein matching the differential samples comprises finding a frequencyoffset of the signal relative to an expected frequency, and whereindecoding the input samples comprises adjusting the decoding of thesamples responsive to the frequency offset.
 12. A method according toclaim 10, wherein decoding the input samples finding correlationsbetween portions of the sequence of input samples and correspondinggroups of symbols, so as to determine the symbols that were transmittedin the stream.
 13. A method for decoding a stream of transmittedsymbols, comprising: receiving a signal in which the symbols are encodedby frequency shift keying; sampling and digitizing the signal togenerate a sequence of input samples; defining a plurality of hypotheseswith respect to a selected group of the symbols occurring in successionin the stream, each such hypothesis comprising a different set ofpossible values of the symbols in the group; finding a respective levelof correlation between each of the plurality of hypotheses and the inputsamples in a portion of the sequence corresponding to the selected groupof the symbols; choosing one of the hypotheses responsive to the levelof correlation thereof; and for at least one of the symbols in theselected group, determining a decoded value of the symbol responsive tothe value of the symbol in the chosen hypothesis.
 14. A method accordingto claim 13, wherein receiving the signal comprises receiving the streamof symbols encoded by Gaussian frequency shift keying.
 15. A methodaccording to claim 13, wherein finding the respective level ofcorrelation comprises determining reference samples that correspond tofrequency shift keying of the symbol values in each of the hypotheses,and correlating the samples in the portion of the sequence with thereference samples.
 16. A method according to claim 15, whereindetermining the reference samples comprises providing coefficients suchthat multiplication of the symbol values in each of the hypotheses bythe coefficients will generate the reference samples, and whereincorrelating the samples comprises multiplying the samples by thecoefficients.
 17. A method according to claim 16, wherein sampling anddigitizing the signal comprises generating complex samples, and whereinmultiplying the samples comprises rotating a phase of each of thecomplex samples responsive to the coefficients.
 18. A method accordingto claim 17, wherein rotating the phase of each of the complex samplesfurther comprises rotating the phase so as to correct for a frequencyoffset of the signal relative to an expected frequency.
 19. A methodaccording to claim 16, wherein the symbols are transmitted at a givensymbol rate, and wherein sampling and digitizing the signal comprisesgenerating the input samples at a sample rate greater than the symbolrate, and wherein determining the reference samples comprisesdetermining the reference samples at the sample rate.
 20. A methodaccording to claim 13, wherein outputting the decoded value of thesymbol comprises outputting the decoded value of a current symbol, andwherein defining the plurality of hypotheses comprises selecting thegroup of the symbols to include at least one symbol preceding thecurrent symbol in the succession and at least one symbol following thecurrent symbol in the succession.
 21. A method according to claim 20,wherein the at least one symbol preceding the current symbol comprisesthree symbols preceding the current symbol, and wherein the at least onesymbol following the current symbol comprises three symbols followingthe current symbol.
 22. A method according to claim 20, whereinselecting the group of the symbols comprises selecting the at least onesymbol preceding the current symbol such that the decoded value of theat least one symbol preceding the current symbol has already beendetermined, and wherein defining the plurality of hypotheses comprisesusing only the hypotheses that comprise the determined value of the atleast one symbol preceding the current symbol.
 23. A method according toclaim 22, and comprising repeating the step of defining the plurality ofhypotheses with respect to the at least one symbol following the currentsymbol, using only the hypotheses that comprise the determined value ofthe current symbol, and repeating with respect to the at least onesymbol following the current symbol the steps of finding the respectivelevel of correlation, choosing one of the hypotheses, and determiningthe decoded value.
 24. A method according to claim 13, wherein choosingthe one of the hypotheses comprises computing a correlation between eachof the plurality of hypotheses and the input samples, and choosing theone of the hypotheses that has a maximal value of the correlationcompared to the other hypotheses.
 25. A method according to claim 13,wherein sampling and digitizing the signal comprises generating complexsamples of the signal, and wherein determining the decoded valuecomprises determining the decoded values of successive first and secondones of the symbols, and comprising comparing a phase difference betweena first one of the samples, corresponding to the first symbol, and asecond one of the samples, corresponding to the second symbol, to adifference between the first and second symbols so as to find afrequency offset of the signal relative to an expected frequency.
 26. Amethod according to claim 25, wherein finding the level of thecorrelation comprises applying a phase rotation to the complex samplesresponsive to the frequency offset.
 27. A method according to claim 13,wherein receiving the signal comprises receiving a packet of datatransmitted from a transmitter to a receiver, the packet ending with afinal symbol, and wherein sampling and digitizing the signal comprisesadding to the samples at the receiver one or more tail samplescorresponding to a tail symbol following the final symbol in the packet,for use in finding the respective level of correlation for thehypotheses used in determining the decoded value of the final symbol.28. A method according to claim 13, wherein receiving the signalcomprises receiving a packet of data transmitted from a transmitter to areceiver, the packet comprising an error correcting code and ending witha final symbol, such that there is an increased level of uncertainty inthe decoded value of the final symbol relative to the other symbols inthe packet, and comprising performing an error check on the packet atthe receiver based on the code in a manner that is insensitive to thedecode value of the final symbol.
 29. A method for decoding a stream oftransmitted symbols, comprising: receiving a signal comprising a packetof data symbols transmitted from a transmitter to a receiver, the packetending with a final symbol; sampling and digitizing the signal togenerate a sequence of input samples; adding to the samples at thereceiver one or more tail samples corresponding to a tail symbolfollowing the final symbol in the packet; and decoding the symbols byprocessing, for each of the symbols, a corresponding portion of thesequence of the samples, such that the portion corresponding to thefinal symbol comprises at least one of the tail samples.
 30. A methodaccording to claim 29, wherein adding the one or more tail samplescomprises identifying one of the input samples as a final sample,derived from the final symbol, and duplicating the final sample.
 31. Amethod according to claim 29, wherein the packet comprises a headerindicating a length of the packet, and wherein adding the one or moretail samples comprises reading the length by decoding the header, andidentifying the final symbol responsive to the length.
 32. A methodaccording to claim 29, wherein decoding the symbols comprises finding,for each of the symbols, a correlation between the corresponding portionof the sequence of the samples and a hypothesis comprising possiblevalues of a group of the symbols.
 33. A method according to claim 29,wherein decoding the symbols comprises processing the samples responsiveto intersymbol interference between the symbols in the received signal.34. A method for decoding a stream of transmitted symbols, comprising:receiving a signal at a transmission frequency, in which signal thesymbols are encoded; sampling and digitizing the signal to generate asequence of complex input samples; processing the samples so as todetermine decoded values of successive first and second ones of thesymbols; computing a phase difference between a first one of thesamples, corresponding to the first symbol, and a second one of thesamples, corresponding to the second symbol; and comparing the phasedifference to a difference between the first and second symbols so as tofind a frequency offset of the transmission frequency relative to anexpected frequency.
 35. A method according to claim 34, whereincomputing the phase difference comprises taking a complex cross productbetween the first and second samples.
 36. A method according to claim34, wherein comparing the phase difference comprises determiningreference samples that correspond to encoding of the first and secondsymbols, and taking a complex cross product between the referencesamples and the first and second samples.
 37. A method according toclaim 34, wherein processing the samples comprises computing acorrelation between a hypothesis comprising possible values of a groupof the symbols, including the first and second symbols, and a portion ofthe sequence of the samples including the first and second samples. 38.A method according to claim 37, wherein computing the correlationcomprises computing a plurality of correlations with respect todifferent hypotheses, and choosing the one of the hypotheses that has amaximal value of the correlation compared to the other hypotheses.
 39. Amethod according to claim 34, and comprising applying a phase rotation,responsive to the frequency offset, to the complex samples subsequent tothe first and second samples in preparation for processing thesubsequent samples to determine the decoded values of the symbols towhich the subsequent samples correspond.
 40. A method according to claim34, wherein receiving the signal comprises receiving the stream ofsymbols encoded by frequency shift keying.
 41. A receiver, for receivinga stream of transmitted symbols that includes a known synchronizationword, the receiver comprising: input circuitry, coupled to receive asignal in which the symbols, including the synchronization word, areencoded by frequency shift keying, and to sample and digitizing thesignal to generate a sequence of input samples; and a synchronizationword detector, coupled to receive the sequence of input samples andadapted to determine, for each of the input samples, a phase differencerelative to a preceding input sample in the sequence, thereby generatinga sequence of differential samples corresponding respectively to theinput samples, and to detect the synchronization word by matching thedifferential samples to the synchronization word.
 42. A receiveraccording to claim 41, wherein the signal comprises a radio frequencysignal having a frequency offset relative to a channel frequencydesignated for the signal, and wherein the synchronization word detectoris adapted to cancel the frequency offset out of the differentialsamples before matching the differential samples to the synchronizationword.
 43. A receiver according to claim 41, wherein the stream ofsymbols is encoded by Gaussian frequency shift keying.
 44. A receiveraccording to claim 41, wherein the symbols are transmitted at a givensymbol rate, and wherein the input circuitry is adapted to sample anddigitize the signal at a sample rate greater than the symbol rate, andwherein the synchronization word detector is adapted to determine thephase difference between pairs of the input samples that are separatedby an interval that is a reciprocal of the symbol rate.
 45. A receiveraccording to claim 41, wherein the synchronization word detectorcomprises at least one multiplier, which is adapted to compute a complexcross product between each of the input samples and the preceding inputsample.
 46. A receiver according to claim 41, wherein thesynchronization word detector is adapted to determine reference samplesthat correspond to frequency shift keying of the synchronization word,and comprises a correlator, which is coupled to correlate the sequenceof differential samples with the reference samples.
 47. A receiveraccording to claim 46, wherein the reference samples are determined bycoefficients provided to the synchronization word detector such thatmultiplication of the symbols in the synchronization word by thecoefficients will generate the reference samples, and wherein thecorrelator is adapted to correlate the sequence of differential sampleswith the reference samples by multiplying the differential samples bythe coefficients.
 48. A receiver according to claim 46, wherein thecorrelator is adapted to compute a sequence of correlation values bycorrelating different, respective portions of the sequence of inputsamples with the synchronization word, and wherein the synchronizationword detector comprises a peak detector, coupled to find a peak valueamong the correlation values of the different portions, thus indicatingthe portion of the sequence of input samples that best matches thesynchronization word.
 49. A receiver according to claim 48, wherein theinput circuitry is adapted to generate complex samples, and wherein thecorrelator is adapted to compute complex correlation values, andcomprising an automatic frequency control circuit, which is adapted tofind a phase angle of the peak correlation value, and a rotator, whichis coupled to the automatic frequency control circuit so as to correct aphase of the input samples of the signal subsequent to thesynchronization word responsive to the phase angle.
 50. A receiveraccording to claim 41, wherein the synchronization word detector isadapted to find a time offset of the input samples relative to thesynchronization word, and comprising a demodulator, which is coupled toreceive the time offset from the synchronization word detector and todecode the input samples of the signal subsequent to the synchronizationword responsive to the time offset.
 51. A receiver according to claim50, wherein the synchronization word detector is adapted to generate aphase offset of the input samples relative to the synchronization word,and comprising an automatic frequency control circuit, which is coupledto find a frequency offset of the signal relative to an expectedfrequency responsive to the phase offset, and wherein the demodulator iscoupled to adjust the decoding of the samples responsive to thefrequency offset.
 52. A receiver according to claim 50, wherein thedemodulator is adapted to find correlations between portions of thesequence of input samples and corresponding groups of symbols, so as todetermine the symbols that were transmitted in the stream.
 53. Areceiver for decoding a stream of transmitted symbols, comprising: inputcircuitry, coupled to receive a signal in which the symbols are encodedby frequency shift keying, and to sample and digitize the signal togenerate a sequence of input samples; and a demodulator, adapted toprocess a plurality of hypotheses with respect to a selected group ofthe symbols occurring in succession in the stream, each such hypothesiscomprising a different set of possible values of the symbols in thegroup, the demodulator comprising: a correlator, adapted to find arespective level of correlation between each of the plurality ofhypotheses and the input samples in a portion of the sequencecorresponding to the selected group of the symbols; and a selector,adapted to choose one of the hypotheses responsive to the level ofcorrelation thereof, so as to determine, for at least one of the symbolsin the selected group, a decoded value of the symbol responsive to thevalue of the symbol in the chosen hypothesis.
 54. A receiver accordingto claim 53, wherein the stream of symbols is encoded by Gaussianfrequency shift keying.
 55. A receiver according to claim 53, whereinthe demodulator is operative to determine reference samples thatcorrespond to frequency shift keying of the symbol values in each of thehypotheses, and wherein the correlator is coupled to correlate thesamples in the portion of the sequence with the reference samples.
 56. Areceiver according to claim 55, wherein the demodulator is adapted todetermine the reference samples by providing coefficients such thatmultiplication of the symbol values in each of the hypotheses by thecoefficients will generate the reference samples, and wherein thecorrelator comprises at least one multiplier, which is coupled tomultiply the samples by the coefficients.
 57. A receiver according toclaim 56, wherein the input circuitry is adapted to generate complexsamples, and wherein the at least one multiplier comprises a complexmultiplier, which is coupled to rotate a phase of each of the complexsamples responsive to the coefficients.
 58. A receiver according toclaim 57, wherein the multiplier is further coupled to rotate the phaseso as to correct for a frequency offset of the signal relative to anexpected frequency.
 59. A receiver according to claim 56, wherein thesymbols are transmitted at a given symbol rate, and wherein the inputcircuitry is adapted to sample and digitize the signal at a sample rategreater than the symbol rate, and wherein the demodulator is adapted todetermine the reference samples at the sample rate.
 60. A receiveraccording to claim 53, wherein the decoded value of the symbol comprisesthe decoded value of a current symbol, and wherein the selected group ofthe symbols comprises at least one symbol preceding the current symbolin the succession and at least one symbol following the current symbolin the succession.
 61. A receiver according to claim 60, wherein the atleast one symbol preceding the current symbol comprises three symbolspreceding the current symbol, and wherein the at least one symbolfollowing the current symbol comprises three symbols following thecurrent symbol.
 62. A receiver according to claim 60, wherein the groupis selected such that the decoded value of the at least one symbolpreceding the current symbol has already been determined, and whereinthe demodulator is arranged to process only the hypotheses that comprisethe determined value of the at least one symbol preceding the currentsymbol.
 63. A receiver according to claim 62, wherein the demodulator isfurther arranged, after determining the decoded value of the currentsymbol, to decode the at least one symbol following the current symbolusing only the hypotheses that comprise the determined value of thecurrent symbol.
 64. A receiver according to claim 53, wherein theselector is adapted to select the one of the hypotheses that has amaximal value of the correlation level compared to the other hypotheses.65. A receiver according to claim 53, wherein the input circuitry isadapted to generate complex samples of the signal, and wherein thedemodulator is operative to determine the decoded values of successivefirst and second ones of the symbols, and comprising an automaticfrequency control circuit, which is coupled to compare a phasedifference between a first one of the samples, corresponding to thefirst symbol, and a second one of the samples, corresponding to thesecond symbol, to a difference between the first and second symbols soas to find a frequency offset of the signal relative to an expectedfrequency.
 66. A receiver according to claim 65, and comprising at leastone rotator, which is coupled to apply a phase rotation to the complexsamples responsive to the frequency offset.
 67. A receiver according toclaim 53, wherein the signal comprises a packet of data transmitted froma transmitter to a receiver, the packet ending with a final symbol, andwherein the demodulator is adapted to add to the samples that are inputto the correlator one or more tail samples corresponding to a tailsymbol following the final symbol in the packet, for use in finding therespective level of correlation for the hypotheses used in determiningthe decoded value of the final symbol.
 68. A receiver according to claim53, wherein the signal comprises a packet of data transmitted from atransmitter to a receiver, the packet comprising an error correctingcode and ending with a final symbol, such that there is an increasedlevel of uncertainty in the decoded value of the final symbol relativeto the other symbols in the packet, and comprising a processor, adaptedto perform an error check on the packet at the receiver based on thecode in a manner that is insensitive to the decode value of the finalsymbol.
 69. A receiver for decoding a stream of transmitted symbols,comprising: input circuitry, coupled to receive a signal comprising apacket of data symbols transmitted from a transmitter to a receiver, thepacket ending with a final symbol, and to sample and digitize the signalto generate a sequence of input samples; and demodulation circuitry,which is adapted to add to the samples one or more tail samplescorresponding to a tail symbol following the final symbol in the packet,and to decode the symbols by processing, for each of the symbols, acorresponding portion of the sequence of the samples, such that theportion corresponding to the final symbol comprises at least one of thetail samples.
 70. A receiver according to claim 69, wherein the receiveris adapted to identify one of the input samples as a final sample,derived from the final symbol, so that the demodulation circuitryduplicates the final sample to serve as the one or more tail samples.71. A receiver according to claim 69, wherein the packet comprises aheader indicating a length of the packet, and comprising a processor,which is adapted to read the length by decoding the header, so as toidentify the final symbol responsive to the length.
 72. A receiveraccording to claim 69, wherein the demodulator is adapted to find, foreach of the symbols, a correlation between the corresponding portion ofthe sequence of the samples and a hypothesis comprising possible valuesof a group of the symbols.
 73. A receiver according to claim 69, whereinthe demodulator is adapted to decode the samples responsive tointersymbol interference between the symbols in the received signal. 74.A receiver for decoding a stream of transmitted symbols, comprising:input circuitry, coupled to receive a signal at a transmissionfrequency, in which signal the symbols are encoded, and to sample anddigitize the signal to generate a sequence of complex input samples; ademodulator, which is coupled to process the samples so as to determinedecoded values of successive first and second ones of the symbols; andan automatic frequency control circuit, which is adapted to compute aphase difference between a first one of the samples, corresponding tothe first symbol, and a second one of the samples, corresponding to thesecond symbol, and to compare the phase difference to a differencebetween the first and second symbols so as to find a frequency offset ofthe transmission frequency relative to an expected frequency.
 75. Areceiver according to claim 74, wherein the automatic frequency controlcircuit comprises a complex multiplier, which is coupled to take acomplex cross product between the first and second samples so as todetermine the phase difference therebetween.
 76. A receiver according toclaim 74, wherein the automatic frequency control circuit is adapted todetermine reference samples that correspond to encoding of the first andsecond symbols, and comprises a complex multiplier, which is coupled totake a complex cross product between the reference samples and the firstand second samples so as to find the frequency offset.
 77. A receiveraccording to claim 74, wherein the demodulator is adapted to decode thesymbols by computing a correlation between a hypothesis comprisingpossible values of a group of the symbols, including the first andsecond symbols, and a portion of the sequence of the samples includingthe first and second samples.
 78. A receiver according to claim 77,wherein the demodulator is adapted to compute a plurality ofcorrelations with respect to different hypotheses, and to choose the oneof the hypotheses that has a maximal value of the correlation comparedto the other hypotheses.
 79. A receiver according to claim 74, andcomprising a rotator, which is coupled to apply a phase rotation,responsive to the frequency offset, to the complex samples subsequent tothe first and second samples in preparation for processing thesubsequent samples to determine the decoded values of the symbols towhich the subsequent samples correspond.
 80. A receiver according toclaim 74, wherein the stream of symbols are encoded by frequency shiftkeying.